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complete, high speed 16-bit a/d converters ad1376/ad1377 rev. d in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 481. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features complete 16-b i t converters w i th reference a n d clock 0.003% maxi mum nonlinea rity no missing codes to 14 bits o v er temperature fast conversion 17 s to 16 bits (ad1 376) 10 s to 16 bits (ad1 377) short cy cle capability adjustable clock rate parallel output s low power 645 mw typica l (ad 1376 ) 585 mw typica l (ad 1377 ) industry-st a nd ard pino ut general description the ad1376 /ad1377 a r e hig h r e s o l u tio n , 16-b i t a n alog-t o- dig i t a l con v er te rs wi t h i n ter n a l r e fer e n c e, clo c k, a nd las e r - tr imm e d t h in-f i l m a p p l ica t io n s r e sis t o r s. the ad1376/ad1377 a r e exce l l en t fo r us e in h i g h r e s o l u t i o n a p pl ic a t io n s r e q u ir i n g m o der a te sp e e d a nd hig h acc u r a c y o r st a b i l i t y o v er co mmer c ia l t e m p era t ur e ra ng es (0c t o 70c). th e y a r e p a cka g e d i n co m p ac t 32-le ad , cera mic s e am-s eale d (her met i c), d u al in-line pa c k a g e s (d ip). t h in - f ilm scalin g r e si s t o r s p r o v i d e b i po la r in p u t ra n g es o f 2.5 v , 5 v , and 10 v an d uni p ola r in p u t ra n g es o f 0 v t o +5 v , 0 v t o +10 v , an d 0 v t o +20 v . d i g i t a l output d a t a i s prov i d e d i n p a r a l l el f o r m w i t h co r r esp o n d in g clo c k an d st a t us o u t p uts. al l dig i t a l i n p u ts and output s are t t l- c o m p a t ibl e . f o r th e ad1376 , th e s e r i al o u t p u t f u n c t i o n is no lo n g er a v a i la b l e a f t e r da t e co de 0111. f o r th e ad1377, th e s e r i al o u t p u t f u n c tion is n o lo n g er a v a i la b l e a f t e r da t e co de 0210. the o p tion o f a p p l yin g an ext e r n al c l o c k o n th e c o nve r t s t ar t p i n t o s l o w do wn t h e in t e r n al l y s e t co n v ersio n t i m e is n o lo n g er s u p p o r t e d fo r ei t h er p a r t . product highlights 1. the ad1376 /ad1377 p r o v ide 16-b i t r e s o l u tion wi t h a maxim u m l i near i t y er r o r o f 0. 003% (1/2 ls b 14 ) a t 25c. 2. the ad1376 con v ersio n t i m e is 14 s (typ ical) s h o r t c y c l ed t o 14 b i ts , a nd 1 6 s t o 16 b i ts . 3. the ad1377 con v ersio n t i m e is 8 s (typ ical) sh o r t c y c l ed t o 14 b i ts , a nd 9 s t o 16 b i ts . 4. t w o b i na r y c o des a r e a v ai lab l e on t h e dig i t a l o u t p ut. the y a r e c s b (co m p l em en ta r y s t ra ig h t b i n a r y ) f o r un i p ol a r i n p u t v o l t a g e ra n g es a n d co b (co m p l em en ta r y o f fset b i n a r y ) f o r b i p o la r in p u t ran g es. c o m p lemen t a r y tw os co m p lemen t (ct c ) co din g ma y b e ob taine d b y in ver ting pin 1 (m s b ) . 5. th e ad1376/a d 1377 in c l ude i n t e r n al r e f e r e n c e a n d c l o c k wi th ext e r n al c l oc k ra t e ad j u s t p i n , a n d p a ralle l digi tal o u t p u t s . func tio n a l block di agram 00 69 9- 0 0 1 (m sb ) b i t 1 1 bi t 2 2 bi t 3 3 bi t 4 4 bi t 5 5 bi t 6 6 bi t 7 7 bi t 8 8 bi t 9 9 bi t 10 10 bi t 11 11 bi t 12 12 (lsb fo r 1 3 b i t s ) b i t 1 3 13 (lsb fo r 1 4 b i t s ) b i t 1 4 14 bi t 15 15 bi t 16 16 s h o r t cy cl e 32 c o n ver t st a r t 31 + 5 v d c s u ppl y v l 30 ga in a d j u s t 29 + 1 5 v d c su ppl y v cc 28 co m p ar a t o r i n 27 b i po l a r o f f s et 26 + 10v 25 + 20v 24 c l k rat e ct rl 23 a nal o g co m m o n 22 ?15v dc s u p p l y v ee 21 c l o ck o u t 20 d i gita l c o m m on 19 s t at us 18 nc 17 16- bi t dac 1 6 - b it s a r cl o c k re f e re nce co m p arat o r 7. 5 k ? 3. 75k ? 3. 75k ? a d 1376/ a d 1377 fi g u r e 1 .
ad1376/ad1377 rev. d | page 2 of 12 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 description of operation ................................................................ 6 gain adjustment .......................................................................... 6 zero offset adjustment ............................................................... 6 timing ............................................................................................ 7 digital output data ..................................................................... 7 input scaling ..................................................................................7 calibration (14-bit resolution examples) .................................8 grounding, decoupling, and layout considerations ..............9 clock rate control ........................................................................9 high resolution data acquisition system .............................. 10 applications ..................................................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 6/05rev. c to rev. d updated format..................................................................universal updated outline dimensions ....................................................... 12 6/03rev. b to rev. c removed serial output function and adjustable clock rate ........................................................universal updated format..................................................................universal changes to general description .................................................... 1 changes to product highlights....................................................... 1 changes to functional block diagram.......................................... 1 inserted esd warning ..................................................................... 3 change to ordering guide.............................................................. 3 change to figure 7 ........................................................................... 5 deleted text from digital output data.......................................... 5 deleted figure 9 and renumbered remainder of figures.......... 5 deleted the using the ad1376 or ad1377 at slower conversion times section ............................................... 8 deleted figure 16.............................................................................. 8 change to figure 13 ......................................................................... 9 change to figure 14 ......................................................................... 9 updated outline dimensions ....................................................... 10
ad1376/ad1377 rev. d | page 3 of 12 specifications typical at t a = 25c, v s = 15 v, +5 v, unless otherwise noted. table 1. ad1376jd/ad1377jd ad1376kd/ad1377kd model min typ max min typ max unit resolution 16 16 bits analog inputs voltage ranges bipolar 2.5 2.5 v 5 5 v 10 10 v unipolar 0 to 5 0 to 5 v 0 to 10 0 to 10 v 0 to 20 0 to 20 v impedance (direct input) v 0 v to +5 v, 2.5 v 1.88 1.88 k? 0 v to +10 v, 5.0 v 3.75 3.75 k? 0 v to +20 v, 10 v 7.50 7.50 k? digital inputs 1 convert command trailing edge of positive 50 ns (min) pulse logic loading 1 1 ls ttl load transfer characteristics 2 (accuracy) gain error 0.05 3 0.2 0.05 3 0.2 % offset error unipolar 0.05 3 0.1 0.05 3 0.1 % of fsr 4 bipolar 0.05 3 0.2 0.05 3 0.2 % of fsr linearity error (max) 0.006 0.003 % of fsr inherent quantization error 1/2 1/2 lsb differential linearity error 0.003 0.003 % of fsr power supply sensitivity 15 v dc (0.75 v) 0.0015 0.0015 % of fsr/% ?v s +5 v dc (0.25 v) 0.001 0.001 % of fsr/% ?v s conversion time 5 12 bits (ad1376) 11.5 13 11.5 13 s 14 bits (ad1376) 13.5 15 13.5 15 s 16 bits (ad1376) 15.5 17 15.5 17 s 14 bits (ad1377) 8.75 8.75 s 16 bits (ad1377) 10 10 s power supply requirements analog supplies +14.5 +15 + 15.5 +14.5 +15 +15.5 v dc ?14.5 ?15 ?15.5 ?14.5 ?15 ?15.5 v dc digital supply +4.75 +5 +5.25 +4.75 +5 +5.25 v dc ad1376 power consumption 600 800 600 800 mw +15 v supply drain +10 +10 ma ?15 v supply drain ?23 ?23 ma +5 v supply drain +18 +18 ma ad1377 power consumption 600 800 600 800 mw +15 v supply drain +10 +10 ma ?15 v supply drain ?23 ?23 ma +5 v supply drain +18 +18 ma warm-up time 1 1 minutes
ad1376/ad1377 rev. d | page 4 of 12 ad1376jd/ad1377jd ad1376kd/ad1377kd model min typ max min typ max unit drift 6 gain 15 5 15 ppm/c offset unipolar 2 4 2 4 ppm of fsr/c bipolar 10 3 10 ppm of fsr/c linearity 2 3 0.3 2 ppm of fsr/c guaranteed no missing code temperature range 0 to 70 (13 bits) 0 to 70 (14 bits) c digital output 1 (all codes complementary) parallel output codes 7 unipolar csb csb bipolar cob, ctc 8 cob, ctc 8 output drive 5 5 lsttl loads status logic 1 during conversion logic 1 during conversion status output drive 5 5 lsttl loads internal clock 9 clock output drive 5 5 lsttl loads frequency 1040/1750 1040/1750 khz temperature range specification 0 to 70 0 to 70 c operating ?25 to +85 ?25 to +85 c storage ?55 to +125 ?55 to +125 c 1 logic 0 = 0.8 v max; logic 1 = 2.0 v mi n for inputs. for digital outputs, lo gic 0 = 0.4 v max. logic 1 = 2.4 v min. 2 tested on 10 v and 0 v to +10 v ranges. 3 adjustable to zero. 4 full-scale range. 5 conversion time may be shortened with short cycle set for lower resolution. 6 guaranteed but not 100% production tested. 7 csbCcomplementary straight binary. cobCcomplementary offset binary. ctcCc omplementary twos complement. 8 ctc coding obtained by inverting msb (pin 1). 9 with pin 23, clock rate controls tied to digital ground.
ad1376/ad1377 rev. d | page 5 of 12 absolute maximum ratings table 2. p a r a m e t e r r a t i n g supply voltage 18 v logic supply voltage +7 v analog inputs (pin 24 and pin 2 5 ) 25 v analog ground to digital ground 0.3 v digital inputs ?0.3 v to v dd + 0.3 v junction tempe r ature 175c storage temperature 150c lead temperature (10 sec) 300c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (electrostatic discharge) sensitive device. electrosta tic char ges as high as 4000 v readily ac cumulate on the human body and test eq uipment and c a n d i scharge wit h out d e tection. although th is product features proprietary esd protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharge s . ther efore, pro p er esd precautions are rec o m m ended to avoid performan c e degradation or l o ss of functiona l ity.
ad1376/ad1377 rev. d | page 6 of 12 description of operati o n 0.0135 0.0080 0.0195 0.0120 0 ?0.0120 ?0.0195 0.0060 0.0030 0 ?0.0030 ?0.0060 ?0.0080 ?0.0135 02 5 7 0 00699-002 temperature ( c) line arity e rro r (% fs r) ad1376/ad1377kd 2ppm/ c, 0.003%, @ 25 c ad1376/ad1377jd 3ppm/ c, 0.006%, @ 25 c f i gure 2. li ne ar it y e r r o r v s . t e mpe r atu r e 0.100 ad1376 0.001 0.003 0.006 0.010 5 1 01 52 00699-003 conversion time ( s) line arity and diffe re ntial line arity e rror (% of fs r) 0 short cycled to 12 bits 1/2lsb 12-bit 1/2lsb 13-bit 1/2lsb 14-bit short cycled to 13 bits short cycled to 14 bits f i g u re 3. a d 13 76 n o nl ine a r i t y v s . co nvers i on tim e 0.100 0.038 ?0.038 0 ?0.068 0.068 0 ?0.100 0 60 50 40 30 20 10 00699-004 7 0 g a in drift e rro r (% fs r) f i g u re 4. g a in d r if t e r r o r v s . t e mpe r at u r e on r e cei p t o f a co nver t s t ar t comman d , th e ad1376/ ad1377 con v er t the v o l t a g e a t t h e a n alog in p u t in t o an e q u i v a l e nt 1 6 - b i t b i n a r y nu m b e r . t h i s c o nv e r s i o n i s acco m p lish e d as fol l o w s: th e 16 -b i t s u cces s i v e a p p r o x ima t ion r e g i s t er (sar) has i t s 16-b i t o u t p u t s co nn e c te d bo t h t o t h e de vice b i t o u t p ut p i n s and to t h e co r r esp o nding b i t in p u ts o f t h e f eed back d a c. the a n alog in p u t is s u cces s i v e l y co m p a r ed t o t h e fe e d b a ck d a c o u t p ut, on e hi t a t a t i m e (m s b f i rs t, ls b las t ). the decisio n t o k e ep o r r e je ct ea ch b i t i s t h en m a de a t th e c o m p l e t i on of e a ch bit c o m p ar i s on p e r i o d , d e p e n d i n g on t h e s t at e o f t h e c o m p a r at o r at t h a t t i m e . gain adjus t ment the ga in ad j u s t m e n t cir c u i t con s is ts o f a 100 p p m/c p o ten - t i o m et er co nn e c t e d acr o s s v s wi t h i t s slider c o nn e c te d thr o ug h a 300 k? r e sis t o r t o p i n 29 (gain ad j) as s h o w n in fi g u r e 5 . i f n o ext e r n al tr im ad j u s t m e n t is desir e d , p i n 2 7 (c o m p a r a t o r in) an d pi n 2 9 ca n b e lef t op en. 00699-005 ad1376/ad1377 29 0.01 f 300k ? +15v 10k ? to 100k ? 100ppm/ c ?15v f i g u re 5. g a in adjus t ment ci r c u i t ( 0. 2% fsr ) zero offset adjustm e nt th e zer o o f fs et ad j u s t m e n t ci r c ui t co n s i s t s o f a 100 p p m /c p o te n t i o me te r c o n n e c te d a c ro ss v s wi th i t s s l i d e r co nn ec t e d thr o ug h a 1. 8 m ? r e sis t o r t o pin 27 f o r al l ran g es . a s sho w n in f i gur e 6, t h e t o le ra n c e o f thi s f i xed r e s i s t o r is n o t cri t ical; a ca rb o n com p os i t ion typ e i s ge n e r a l l y a d e q u a te. u s i n g a ca r b on c o m p o - si t i on resis t o r ha vin g a ?120 0 p p m/c t e m p era t u r e c o ef f i cien t con t r i b u tes a w o rs t-cas e o f fs et t e m p er a t ur e co ef f i cien t of 32 l s b 14 61 p p m/ls b 14 120 0 p p m/c = 2. 3 p p m /c o f fs r , if t h e o f fs et a d j u st me n t p o te n t iome ter is s e t a t e i t h er e n d o f i t s a d j u st me n t ra n g e . si nce t h e max i m u m o f fs et ad j u s t me n t r e quire d i s typi cal l y n o m o re than 16 l s b 14 , us e of a car b on com p o s i t ion o f f s et s u mmin g r e sist or ty p i c a l l y con t r i b u t e s no m o re t h an 1 p p m /c of fs r o f fs et te m p era t ur e c o ef f i ci e n t. 00699-006 ad1376/ad1377 27 1.8m ? +15v 10k ? to 100k ? ? 15v f i g u re 6. zero o f f s e t adjus t ment ci r c u i t (0. 3% fsr ) an al t e r n a t e o f fs et ad j u s t m e n t c i r c ui t, w h ich con t r i b u t e s a n e g l ig i b le o f fs et t e m p era t ur e co ef f i cien t if m e t a l f i lm r e sis t o r s (t em p e r a t u r e c o ef f i cien t <100 p p m/c) a r e us ed , is sh o w n in fi g u r e 7 . 00699-007 ad1376/ad1377 27 22k ? m.f. 180k ? m.f. 180k ? m.f. +15v 10k ? to 100k ? offset adj ?15v f i gure 7. l o w t e mper atu r e co effici ent zer o adjustm e nt ci r c u i t
ad1376/ad1377 rev. d | page 7 of 12 i n e i t h er ad j u st m e n t cir c u i t, t h e f i xe d r e sisto r co nn e c te d to pin 27 sh o u ld b e lo ca te d clo s e to t h is p i n to k e e p t h e pin co nn e c t i o n sh o r t. p i n 27 is q u i t e s e n s i t i v e t o ex t e r n al n o is e p i ck u p and sh ou ld b e g u a r de d b y a n alo g c o mmon. timi ng the timin g dia g ra m is sh o w n in f i gur e 8. re cei p t o f a c o nver t st ar t sig n a l s e ts t h e st a t us f l ag, i ndic a t i n g co n v ersio n in pr og r e ss. this in t u r n r e m o v e s t h e in h i b i t a p plie d to t h e g a te d cl o c k , p e r m i t t i ng i t to r u n t h rou g h 1 7 c y cl e s . a l l t h e s a r p a ral l e l b i ts, t h e st a t us f l i p -f lo ps, a nd t h e ga te d clo c k inhi b i t sig n al a r e ini t i a li ze d o n t h e t r a i l i n g e d g e o f t h e c o nver t st ar t sig n a l . a t t i me t 0 , b 1 is r e s e t a nd b 2 Cb 16 are se t un c o n d i t i o nall y . a t t 1 , t h e bi t 1 de cisio n is m a de (k e e p) an d bi t 2 is r e s e t u n co ndi t i o n a l ly . this s e q u e n ce con t i n ues un t i l t h e b i t 16 (ls b ) dec i sio n (k eep) is made a t t 16 . th e s t a t us f l a g is r e s e t, indic a t i n g tha t t h e con v ersio n is co m p lete a nd tha t t h e p a r a l l e l outp ut d a t a i s v a l i d. r e s e tt i n g t h e s t a t u s f l a g re s t or e s t h e g a t e d clo c k i n hib i t sig n al , for c in g t h e clo c k o u t p ut t o t h e lo w l o g i c 0 s t a t e . n o te tha t t h e c l o c k r e ma ins lo w un t i l t h e n e x t co n v ersio n . c o r r esp o ndi n g p a r a l l el d a t a b i t s b e com e va li d o n t h e s a m e pos i ti v e - g o i n g c l oc k ed g e . 00699- 008 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 (3) (2) (1) 0 1 10 0 1 11 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 0 msb status internal clock convert start bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 lsb lsb msb maximum throughput time conversion time (2) notes: 1. the convert start pulsewidth is 50ns min and must remain low during a conversion. the conversion is initiated by the trailing edge of the convert command. 2. msb decision. 3. clock remains low after last bit decision. f i gur e 8 . tim i ng dia g r a m (bi n a r y co de 01 100 11 101 11 101 0 ) digi tal ou tput da ta p a ralle l da ta f r o m t t l s t o r a g e r e gi s t e r s i s in n e ga ti v e tr ue f o rm (l og ic 1 = 0 v a nd l o g i c 0 = 2.4 v). p a ral l e l da t a o u t p u t co din g is co m p le m e n t ar y b i na r y fo r un i p ola r r a n g es and co m p le m e n t - ta r y o f fset b i n a r y f o r b i p o la r ra n g es. p a ralle l da ta beco m e s valid a t leas t 20 n s bef o r e th e s t a t us f l a g r e t u r n s t o l o g i c 0, p e r m i t tin g p a ra l l e l da t a tra n sf er t o be c l o c k e d on t h e 1 t o 0 tra n si tio n o f t h e s t a t us f l a g (s ee f i gur e 9). p a ral l e l da t a ou t p ut change s st a t e on p o s i t i ve going cl o c k e d ge s . 00699-009 bit 16 valid busy (status) 20ns min to 90ns f i gure 9. lsb v a lid to status l o w short cycl e in put p i n 32 (s h o r t cy cle) p e r m i t s t h e t i min g c y cle sh o w n in f i g u re 8 to b e te r m i n a t e d af te r a n y n u mb e r of d e s i re d bi t s h a s be e n con v er t e d , al lo win g s o me wha t sh o r t e r co n v ersio n t i m e s in a p plic a t io n s n o t r e q u ir in g f u l l 1 6 -b i t r e s o l u t i o n . w h en 10 -b i t r e s o l u t i o n is des i r e d , pi n 32 is c o nn e c te d to bi t 11 o u t p u t p i n 11. th e con v ersio n c y cle t h en t e r m ina t es and t h e st a t us f l a g r e s e ts a f t e r th e bi t 10 decisio n (f igur e 8). sh o r t c y c l e co nn ec t i o n s and as s o c i a t e d 8-, 10-, 12-, 13-, 14 -, a nd 15-b i t co n v ersio n t i m e s a r e s u mma r i ze d i n t a b l e 3 fo r a 1.6 mh z c l o c k (ad1377) o r 933 kh z c l o c k (ad1376). table 3. short cycle co nnections resolution maximum conversion ti me (s) bits (% f s r ) a d 1 3 7 7 ad13 7 6 status flag reset connect short cycle pin 32 to 1 6 0 . 0 0 1 5 1 0 1 7 . 1 t 16 nc (open) 1 5 0 . 0 0 3 9 . 4 1 6 . 1 t 15 pin 16 1 4 0 . 0 0 6 8 . 7 1 5 . 0 t 1 pin 15 1 3 0 . 0 1 2 8 . 1 1 3 . 9 t 13 pin 14 1 2 0 . 0 2 4 7 . 5 1 2 . 9 t 12 pin 13 1 0 0 . 1 0 0 6 . 3 1 0 . 7 t 10 pin 11 8 0 . 3 9 0 5 . 0 8 . 6 t 8 pin 9 inpu t scali n g the ad c i n p u t s s h o u l d b e s c al e d as clos e t o t h e maxim u m in p u t sig n al ra ng e as p o s s i b le t o us e t h e maxi m u m sig n al re s o lut i on of t h e a d c . c o n n e c t t h e i n put s i g n a l a s s h ow n i n t a b l e 4. s e e f i g u r e 10 f o r cir c ui t deta ils.
ad1376/ad1377 rev. d | page 8 of 12 ta ble 4. i nput sca l i n g conn ect i ons input signal line output code connect pin 26 to connect pin 24 to connect input signal to 10 v cob pin 27 1 input signal pin 24 5 v cob pin 27 1 o p e n p i n 2 5 2.5 v cob pin 27 1 pin 27 1 pin 25 0 v to +5 v csb pin 22 pin 27 1 pin 25 0 v to +10 v csb pin 22 open pin 25 0 v to +20 v csb pin 22 input signal pin 24 1 pi n 27 i s ext r em e l y s e n s i t i v e t o n o i s e a n d sh ou ld be g u a r ded by an alog c o mmon . 00699-010 22 analog common 26 bipolar offset comp in 24 25 27 7.5k ? r2 3.75k ? 10v span 20v span r1 3.75k ? from dac comparator to sar v ref f i gure 1 0 . input s c a l i n g cir c ui t calibration ( 14-bit resolution examples) ext e rn al z e r o ad j u s t m e n t a n d ga i n ad j u s t m e n t po t e n t i o m e t e r s , co nn e c te d as sho w n i n f i gur e 5 a nd f i gur e 6, ar e us e d fo r de vice ca l i b r a t i o n. t o p r e v en t i n ter a c t ion o f t h es e t w o ad j u st m e n t s, ze r o is a l wa y s ad j u st e d f i rst and t h e n ga in . z e r o i s ad j u ste d wi t h t h e a n a l o g in pu t ne a r t h e m o st ne ga t i ve e nd o f t h e a n alog ra n g e (0 f o r un i p o l a r a n d min u s f u ll sca l e f o r b i p o la r in p u t ra n g es). ga i n is ad j u st e d wi t h t h e a n a l og in p u t n e a r t h e m o s t posi ti v e en d o f th e a n alog ra n g e . 0 v to 10 v r a nge s e t a n alog in p u t t o +1 ls b 14 = 0.00061 v . a d j u st zer o f o r dig i tal o u t p u t = 11111111111110. z e ro is n o w cal i b r a t ed . s e t a n alog in p u t t o +fs r ? 2 ls b = 9.99878 v . a d j u st ga in f o r 00000000000001 dig i tal o u t p u t co de; f u l l s c ale ( g a i n) is n o w cal i b r a t ed. h a lf -s cal e cal i b r a t ion c h ec k: s e t a n a l og in p u t t o 5.00000 v ; dig i t a l o u t p u t co de sh o u ld be 01111 111111111. ?10 v to +10 v range s e t a n a l og in p u t t o ?9.99 878 v ; ad j u s t zer o f o r 1 111111111 110 d i g i tal o u t p u t (co m p l em e n ta r y o f fse t b i na r y ) co d e . s e t a n alog in p u t t o 9 . 99756 v ; ad j u s t ga in fo r 000000000 00 001 dig i t a l o u t p u t (co m p l em en ta r y o f fse t b i n a r y ) co d e . h a lf- s cale cal i b r a t ion check: s e t a n alog in p u t t o 0.0000 0 v ; dig i tal ou t p u t (co m p l emen ta r y o f fs et b i na r y ) co de sho u l d be 011111111 1111 1. 00699- 011 ? 15v +15v a 16-bit successive appromixation register 16-bit dac ref control 3. 75k ? 3. 75k ? 24 26 23 19 29 28 22 21 25 e in (0v to +10v) i in keep/ reject 7.5k ? +15v ? 15v zero adj 10k ? to 100k ? 27 i os = 1.3ma ad1376/ ad1377 1.8m ? 1 f +5v + 30 + 1 f + 1 f +15v ? 15v gain adj 10k ? to 100 k ? 300k ? 0.01 f note: a nalog ( ) and digital ( ) grounds are not tied internally and must be connected externally . f i gur e 1 1 . a n al o g and p o we r co nne c tio n s f o r u n ipo l a r 0 v t o 10 v input r a ng e 00699-012 ?15v +15v a 16-bit successive appromixation register 16-bit dac ref control 3.75k ? 3.75k ? 24 26 23 19 29 28 22 21 25 e in (?10v to +10v) i in keep/ reject 7.5k ? +15v ?15v zero adj 10k ? to 100k ? 27 i os = 1.3ma ad1376/ ad1377 1.8m ? 1 f +5v + 30 + 1 f + 1 f +15v ?15v gain adj 10k ? to 100k ? 300k ? 0.01 f note: a nalog ( ) and digital ( ) grounds are not tied internally and must be connected externall y f i gur e 1 2 . a n al o g and p o we r co nne c tio n s for b i po la r ?1 0 v to +1 0 v i n put ra nge other ranges rep r es en t a ti v e dig i tal co din g f o r 0 v t o +10 v a nd ?10 v t o +10 v ra n g es is g i v e n in t h e 0 v t o 10 v r a n g e s e c t io n and ?10 v t o +10 v r a n g e s e c t io n. c o din g re l a tio n s h i p s and cali b r a t io n p o in ts f o r 0 v t o +5 v , ?2.5 v t o +2.5 v , an d ?5 v to + 5 v r a nge s c a n b e f o u n d b y h a l v i n g prop or t i on a l ly t h e co r r es p o n d in g co de eq u i valen t s lis t ed f o r the 0 v t o +10 v a n d ?10 v t o +10 v ra n g es, r e s p ec tiv e l y , as indica t e d in t a b l e 5.
ad1376/ad1377 rev. d | page 9 of 12 table 5. transition valu es vs. calibration codes ou tpu t cod e msb lsb 1 r a n g e 1 0 v 5 v 2.5 v 0 v to +10 v 0 v to +5 v 000 000 2 +full sca l e +10 v +5 v +2.5 v +10 v +5 v ?3/2 lsb ?3/2 lsb ?3/2 lsb ?3/2 lsb ?3/2 lsb 011111 midscale 0 v 0 v 0 v +5 v +2.5 v C1/2 lsb C1/2 lsb C1/2 lsb C1/2 lsb C1/2 lsb 111110 ?full scale ?10 v ?5 v ?2.5 v 0 v 0 v +1/2 lsb +1/2 lsb +1/2 lsb +1/2 lsb +1/2 lsb 1 for lsb va lue f o r ra n g e a n d r e so lut i on use d , see ta . ble 6 ta ble 6. i nput volt a g e ra nge a nd lsb va lue s 2 vo lt a g es gi ven a r e t h e n o m i n a l va lue f o r t r a n si t i on t o t h e code sp eci f i e d . analog input v o ltage range 10 v 5 v 2.5 v 0 v to +10 v 0 v to +5 v code designati o n cob 1 or ctc 2 cob 1 or ctc 2 c o b 1 or ctc 2 c s b 3 csb 3 one least signif icant bit (lsb) n 2 fsr n 2 v 20 n 2 v 10 n 2 v 5 n 2 v 10 n 2 v 5 n = 8 78.13 mv 39.06 mv 19.53 mv 39.06 mv 19.53 mv n = 10 19.53 mv 9.77 mv 4.88 mv 9.77 mv 4.88 mv n = 12 4.88 mv 2.44 mv 1.22 mv 2.44 mv 1.22 mv n = 13 2.44 mv 1.22 mv 0.61 mv 1.22 mv 0.61 mv n = 14 1.22 mv 0.61 mv 0.31 mv 0.61 mv 0.31 mv n = 15 0.61 mv 0.31 mv 0.15 mv 0.31 mv 0.15 mv 1 cob = complementary offset binary. 2 c t c = complemen t ary twos c o mpl e m e ntachieved by us ing an inve rte r to co mpl e me nt the m o s t s i gnif icant bit t o prod uce msb . 3 cs b = c o m p lem e n t a ry st ra i g h t bi n a ry z e r o - an d f u l l - s ca le c a lib r a t io n ca n b e ac co m p li sh e d to a p r e c isio n o f a p pr o x ima t e l y 1/2 ls b usin g t h e st a t ic a d j u st m e n t p r o c e d ur e de s c r i b e d p r e v i o u sly . by summin g a sma l l sine o r tri a n g ula r w a v e v o l t a g e w i th t h e si gn al a p p l i e d t o th e a n alog in p u t, t h e o u t p u t ca n be c y c l ed t h r o ug h each o f th e cal i b r a t ion c o de s of i n te re s t to more a c c u r a tely d e te r m i n e t h e c e n t e r ( o r end p o i n ts) o f e a ch di s c r e te quan t i za t i on le vel. a det a i l e d des c r i p t io n o f t h is d y na m i c ca l i b r a t io n te chn i que is p r es en te d in a n alo g - d ig i t a l c o n v e r sion h a ndbo ok , e d i t e d b y d . h. s h ein g old , p r en tice h a l l , i n c., 1 986. grounding, decoup li n g , a n d l a y o u t consi d era t io ns m a n y d a t a a c q u isi t io n com p on e n ts h a ve tw o o r m o r e g r o u nd p i n s t h a t a r e n o t co nne c t e d t o g e t h er w i t h in t h e de vice. th es e g r o u n d s a r e us u a l l y r e f e rr ed t o as d i git a l c o mm o n (log i c p o w e r r e t u r n ), an al o g co mm o n (a nalog p o w e r r e t u r n ), o r a n a l o g sig n a l g r o u nd . t h es e g r o u n d s (pi n 19 and pin 22) m u st be tied t o g e t h er a t o n e p o in t as c l os e as p o s s i b l e t o th e c o n v e r t e r . i d e a ll y , a s i n g le so l i d a n al og gr o u n d p l a n e un d e r th e co n v er t e r w o u l d b e desirab l e . c u r r en t f l o w s t h r o ug h t h e wir e s a nd et ch s t r i p e s o f t h e cir c u i t car d s, a nd si n c e t h es e p a t h s ha v e r e sist a n ce and i n d u c t an ce, h u ndr e d s o f mi l l i v o l ts can b e gen e r a te d b e twe e n t h e sy ste m a n a l o g g r o u n d p o in t an d t h e g r o u n d p i n s o f t h e ad c. s e p a ra t e wide co nd uc to r s t r i p e g r ou nd re tu r n s shou l d b e pro v i d e d f o r h i g h re s o lut i on co n v er t e rs t o minimi ze n o is e and ir los s es f r o m t h e c u r r en t f l o w i n t h e pa th f r o m th e co n v er t e r t o th e sys t em gr o u n d po in t. i n this wa y , ad c s u p p l y c u r r en ts a nd o t h e r dig i tal log i c-ga t e r e t u r n c u r r en t s a r e n o t summ e d i n t o t h e s a m e r e t u r n p a t h as a n alog sig n als w h er e t h e y w o u l d ca us e m e as urem e n t er r o rs. e a ch of t h e a d c su p p ly te r m in a l s shou l d b e c a p a c i t i v e ly de co u p le d as c l os e t o the ad c as p o s s i b le. a larg e val u e (s uc h as 1 f) ca p a ci to r in p a ral l e l wi th a 0.1 f c a p a ci t o r is us ual l y su f f i c i e n t. a n a l o g su p p l i e s are to b e b y p a ss e d to t h e a n a l o g c o mmon (a na lo g p o w e r r e t u r n ) pin 22 an d t h e lo g i c su p p ly i s b y p a s s e d t o d i git a l co mmo n (logic p o w e r r e t u r n ) p i n 19 . the m e t a l co v e r is in t e r n a l ly g r o u n d e d w i t h r e sp e c t t o t h e p o w e r s u p p lie s , g r o u n d s, and e l e c tr ical sig n als. d o n o t ext e r n al l y g r o u nd t h e co v e r . clock rate control the ad1376 /ad1377 ca n be op era t e d a t fas t er co n v ersio n tim e s b y co nn ec ti n g t h e c l ock ra t e co n t r o l (p i n 23) t o a n ext e r n al m u l t i t u r n tr im p o t e n t io m e t e r (t cr <100 p p m /c) as sh ow n i n fi g u re 1 3 . 00699-013 ad1376/ad1377 23 2.25mhz @ 5v 1750khz @ dgnd 15v dc 5k f i gure 13. clock rat e control c i r c u i t
ad1376/ad1377 rev. d | page 10 of 12 high resol u tio n data acquis iti o n s y stem t h e e s sen t i a l d e ta ils o f a h i g h r e so l u ti o n da ta a c q u i s i t i o n syst em usin g a 16- b i t s a m p le-and- h o ld a m plif ier (s h a ) a nd t h e ad1376/ad13 77 a r e s h o w n in f i gur e 14. c o n v ersio n is ini t i a t e d b y t h e fa l l in g e d ge o f t h e c o nver t st ar t p u ls e . this edge dr i v es th e de vice s s t a t us l i n e hig h . the in v e r t er th en d r i v es t h e s h a in t o h o l d m o d e . s t a t u s r e m a i n s hi gh t h r o ug h o u t t h e co n v ersio n and r e t u r n s lo w on c e t h e con v ersio n is co m p let e d . this al lo ws t h e s h a t o r e -en t er t r ac k mo de . this cir c u i t can exhi b i t n o n l i n e a r i t i es a r isin g f r o m t r a n sien ts p r od uced a t t h e a d c s in p u t b y th e fall i n g ed g e o f co n v er t st ar t . this e d ge r e s e ts t h e a d c s in t e r n a l d a c; t h e r e su l t ing t r a n sien t dep e nds o n t h e s h a s p r es en t o u t p ut v o l t a g e an d t h e a d c s pr i o r c o n v e r s i on re su lt . i n t h e c i rc u i t of f i g u re 1 5 , t h e fa l l in g e d ge o f c o nver t st ar t a l s o places t h e sh a in to hold m o de (via t h e ad c s s t a t us o u t p u t ), ca using th e r e s e t t r a n sien t t o o c c u r a t t h e s a m e m o m e n t as t h e s h a s t r ack-and - h o ld tra n si ti o n . t i m i n g s k ew s a n d ca pa ci ti v e co u p li n g ca n ca us e s o me o f t h e t r a n sien t s i g n al t o add t o t h e sig n a l b e i n g acq u ir e d b y th e s h a , i n tr od u c i n g n o n l i n e a ri t y . 00 69 9- 01 4 sh a a d 1376/ a d 1377 30 21 28 22 24 27 26 19 18 31 bi t s 1?16 + co nv e r t s t art ?10v t o + 1 0 v + 10 f + 10 f 10 f +1 5 v ?15v +5 v ana l o g in p u t ? 10 v t o + 1 0 v f i g u re 14. bas i c d a t a ac quis it i o n sy stem i n te r c onne c t ions 16- bit s h a a m u ch s a fer a p p r o a ch is t o ad d a f l i p -f lo p , as sho w n i n f i gur e 15. th e r i sin g e d g e o f c o nver t st a r t places t h e t r ack-and- h o ld de vice in to h o ld m o de b e fo r e t h e ad c r e s e t t r a n sien ts b e g i n. the fal l i n g e d g e o f s t a t us pl aces t h e s h a b a ck i n t o t r ack m o de. s y st em t h r o ug h p u t wi l l b e r e d u ce d if a lo n g c o nver t st ar t p u ls e is us e d . thr o ug h p u t ca n b e calc u l a t e d f r o m cs conv ac t t t throughput + + = 1 w h er e: t ac is t h e t r ack - a nd- h o ld acq u i s i t io n t i m e . t co nv i s th e tim e r e q u i r ed f o r th e a d c co n v e r si o n . t cs i s th e d u r a ti o n o f c o n v e r t s t a r t . the com b ina t ion o f the ad137 6 a nd a 16-b i t s h a can p r o v ide g r e a t e r t h a n 50 khz t h r o ug h p u t . n o sig n if ican t t r ack-and- h o ld d r oo p e r r o r w i ll be in tr o d uced , p r o v i d ed t h e wid t h o f c o nver t st ar t is sm a l l co m p a r e d wi t h t h e ad c s co n v ersio n t i m e . 0 06 99 - 0 15 sh a a d 1376/ a d 1377 30 21 28 22 24 27 26 19 18 31 bi t s 1?1 6 + ?10 v t o + 1 0 v + 10 f + 10 f 10 f + 15v ?15 v +5 v anal o g in p u t ?1 0v t o + 10v co nv e r t s t art hc1 12 s r q j q k +5v f i g u re 15. imp r o v e d d a t a ac quis it i o n sy s t em 1
ad1376/ad1377 rev. d | page 11 of 12 applications the ad1376/ad1377 are excellent for use in high resolution applications requiring moderate speed and high accuracy or stability over commercial (0c to 70c) temperature ranges. typical applications include medical and analytic instrumen- tation, precision measurement for industrial robotics, automatic test equipment (ate), multichannel data acquisition systems, servo control systems, or anywhere wide dynamic range is required. a proprietary monolithic dac and laser-trimmed thin-film resistors guarantee a maximum nonlinearity of 0.003% (1/2 lsb 14 ). the converters may be short cycled to achieve faster conversion times15 s to 14 bits for the ad1376 or 8 s to 14 bits for the ad1377.
ad1376/ad1377 rev. d | page 12 of 12 outline dimensions notes: 1. index area is indicated by a notch or lead one identification mark located adjacent to lead one. 2. controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.023 (0.58) 0.014 (0.36) 0.910 (23.11) 0.890 (22.61) 1 16 17 32 1.728 (43.89) max 0.225 (5.72) max 0.025 (0.64) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) 1.102 (27.99) 1.079 (27.41) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.120 (3.05) max pin 1 indicator (note 1) 0.192 (4.88) 0.152 (3.86) 0.206 (5.23) 0.186 (4.72) 0.025 (0.64) min f i gure 16. 32 l e ad bott om-b r a z e d c e r a mic dip for hybr id [bbdip_h] (dh-32e) di me nsio ns sho w n i n i n che s a n d ( m il lim e t e r s) ordering guide model temperature r a nge maximum line arity e rror conversion ti me (16 bits) package option 1 ad1376jd 0c to 70c 0.006% 17 s dh-32e ad1376kd 0c to 70c 0.003% 17 s dh-32e ad1377jd 0c to 70c 0.006% 10 s dh-32e ad1377kd 0c to 70c 0.003% 10 s dh-32e 1 dh -32e = c e ramic dip . ? 2005 anal og d e v i ces, inc. all ri ghts reserve d . tr ade m a r ks and registered trade m ar ks are the pr op erty of their respective owne rs. c00699C0 C 6/05(d)

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